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Introduction
Finite State Machines
(FSM) are sequential circ
uit used in m
any digital systems
to control the behavior of
systems and dataflow paths. Examples of FSM include control units and sequencers. This lab introduces
the concept of two types of FSMs, Mealy and Moore, and the modeling styles to develop such machines.
Please refer to the Vivado tutorial on how to use the Vivado tool for creating projects and verifying digital
circuits.
Objectives
After completing this lab, you will be able to:
Model Mealy FSMs
Model Moore FSMs
Mealy FSM Part 1
A finite-state machine (FSM) or simply a state machine is used to design both computer programs and
sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite number of
user-defined states. The machine is in only one state at a time; the state it is in at any given time is called
the current state. It can change from one state to another when initiated by a triggering event or condition;
this is called a transition. A particular FSM is defined by a list of its states, and the triggering condition for
each transition.
The behavior of s
tate machines can be obs
erved in m
any devices in m
odern society perf
orm
ing
a predetermined sequence of actions depending on a sequence of events with which they are presented.
Simple examples are vending machines which dispense products when the proper combination of coins
are deposited, elevators which drop riders off at upper floors before going down, traffic lights which
change sequence when cars are waiting, and combination locks which require the input of combination
numbers in the proper order.
The state machines are modeled using two basic types of sequential networks- Mealy and Moore. In a
Mealy machine, the output depends on both the present (current) state and the present (current) inputs.
In Moore machine, the output depends
only on the pres
ent state.
A general model of a Mealy sequential machine consists of a combinatorial network, which generates the
outputs and the next state, and a state register which holds the present state as shown below. The state
register is normally modeled as D flip-flops. The state register must be sensitive to a clock edge. The
other block(s) can be modeled either using the always procedural block or a mixture of the always
procedural block and dataflow modeling statements; the always procedural block will have to be
sensitive to all inputs being read into the block and must have all output defined for every branch in order
to model it as a combinatorial block. The two blocks Mealy machine can be viewed as
Here are the state diagram of a parity checker Mealy machine and the associated model.